1. Technical Field
The embodiments herein generally relate to semiconductor processing and characterization, and more specifically, to an electromigration testing technique for semiconductor devices.
2. Description of the Related Art
The ability to process uniformly across a monolithic substrate and/or across a series of monolithic substrates is advantageous for manufacturing efficiency and cost effectiveness, as well as repeatability and control. However, uniform processing across an entire substrate can be disadvantageous when optimizing, qualifying, or investigating new materials, new processes, and/or new process sequence integration schemes, since the entire substrate is nominally made the same using the same materials, processes and process sequence integration schemes. Each processed substrate generally represents, in essence, only one possible variation per substrate. Thus, the full wafer uniform processing under conventional processing techniques results in fewer data points per substrate, longer times to accumulate a wide variety of data and higher costs associated with obtaining such data.
For example, lifetime and reliability characteristics are a very important specification for any new or existing product. Lifetime and reliability tests are usually tested with accelerated conditions such as high temperature, voltage, longer time, etc. Electromigration (EM) is an important and indispensable reliability test for back end of line (BEOL) application. For any new product or technology node, all wafers with new material and processes generally have to pass EM lifetime criteria before being introduced into a market.
To accurately perform EM tests and evaluate the lifetime of a device, a properly designed test structure is crucial. Although many structures are available, conventional test structures can be divided into two categories. The first category of test structures is characterized by their simplicity and ease of fabrication and includes so-called dog-bone test structures and standard wafer-level EM test structures (SWEAT). The first category of test structures, however, typically can only be used to test the copper line quality and generally are not suitable to evaluate the EM performance of a barrier layer of a via. The second category of test structures is typically suitable to evaluate the EM performance of the barrier layer, but is neither simple nor easy to fabricate. Structures in this second category follow the standard BEOL metal 1 and metal 2 processing by using copper dual damascene flow with advanced lithography and chemical-mechanical planarization (CMP) process. Since they are similar to final products, structures in the second category are generally used to evaluate all potential problems including the barrier layer. However, the device fabrication process is extremely complicated and resource demanding, and it is usually performed in a wafer factory (e.g., fab).
Moreover, using conventional technology to test the EM of a barrier layer, the entire wafer is generally used to evaluate a single process condition. Generally, the conventional unit process and test workflow used in current industry is complicated, time consuming, and not very cost efficient. Currently, each process is performed on one wafer at metal 1 or higher layer. Then, the wafer is passivized and at least four more layers are deposited, or the wafer is packaged, and then reliability testing is performed. To know the result of each condition, one wafer with many follow-up steps is required, which under current technology is very complicated as well as cost inefficient. For example, semiconductor companies conduct research and development (R&D) on full wafer processing through the use of split lots, as the deposition systems are designed to support this processing scheme. This approach has generally resulted in high R&D costs and the inability to conduct extensive experimentation in a timely and cost effective manner.
Generally, for the purpose of evaluating the barrier layer, the available structures are either complicated or not useful. The barrier layer cannot be ignored, however, and is an important component for next generation BEOL systems. In addition, a high performance barrier layer effectively prevents copper diffusion into surrounding dielectrics and significantly increases the lifetime of a device. With the urgent demand of finding the appropriate material and process for next generation barrier layers, a simple and effective EM test structure is required.